Efficeint Design and Implementation of Truncated Paraller Multipliers of Fpga

Multiplication is frequently required in digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word size. Thus an important design goal is to reduce the area requirement of the rounded output multiplier. This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The power and area of a truncated 6×6-bit multiplier shows significant improvement as compared to standard 6×6-bit multiplier. For Xilinx Spartan-3AN (XC3S700ANFGG484-5) FPGA device, truncated multiplier shows a reduction in power and area by 45% and 67%respectively as compared to standard multiplier.